Company Name: Synopsys
Website: www.synopsys.com
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Experience: Freshers
Education: B.Tech / M.Tech
Location: Bangalore
Description
As part of the Solutions Group at Synopsys India, the selected candidate would be working on
one or more aspects of the development of DesignWare family of synthesize cores, including
Specification, Architect, Design, Verification and Release engineering for Synopsys IP products. The domain area of expertise s would span across areas such as AMBA(AHB,AXI), USB3, Gigabit thernet, Mobile storage, MIPI.
Post the orientation and training, the candidate would be assigned to work on either the design or verification tasks based on aptitude and business needs and will be part of a global team of expert Design/Verification Engineers.
On the design side, the candidate would work on System level and RTL based hardware design coding languages such as Verilog, System Verilog, usage of tools for rule checking, Synthesis, timing closures and low power design concepts such as unified power flows.
On the verification side, candidate would work on latest verification methodologies such as UVM, VMM. The verification tasks would include building CRV based complex test environment, test case writing in OOPS based languages such as SystemVerilog, Vera, running tests and debugging failures, Functional coverage implementation and would involve usage of industry standard simulators such as VCS.
It is essential that the individual has the aptitude to work in the VLSI domain area of expertise , has great communication skillfulness and is able to demonstrate great analysis, debug and problem solving skillfulness and be autogenous-driven.
Candidate Profile :
B.Tech or M.Tech in Electrical/Electronics Engineering or allied subjects with minimum qualification
marks of 70 % or CGPA of 7.0 and above, in aggregate of all semesters
Click Here To Apply
Website: www.synopsys.com
Experience: Freshers
Education: B.Tech / M.Tech
Location: Bangalore
Description
As part of the Solutions Group at Synopsys India, the selected candidate would be working on
one or more aspects of the development of DesignWare family of synthesize cores, including
Specification, Architect, Design, Verification and Release engineering for Synopsys IP products. The domain area of expertise s would span across areas such as AMBA(AHB,AXI), USB3, Gigabit thernet, Mobile storage, MIPI.
Post the orientation and training, the candidate would be assigned to work on either the design or verification tasks based on aptitude and business needs and will be part of a global team of expert Design/Verification Engineers.
On the design side, the candidate would work on System level and RTL based hardware design coding languages such as Verilog, System Verilog, usage of tools for rule checking, Synthesis, timing closures and low power design concepts such as unified power flows.
On the verification side, candidate would work on latest verification methodologies such as UVM, VMM. The verification tasks would include building CRV based complex test environment, test case writing in OOPS based languages such as SystemVerilog, Vera, running tests and debugging failures, Functional coverage implementation and would involve usage of industry standard simulators such as VCS.
It is essential that the individual has the aptitude to work in the VLSI domain area of expertise , has great communication skillfulness and is able to demonstrate great analysis, debug and problem solving skillfulness and be autogenous-driven.
Candidate Profile :
B.Tech or M.Tech in Electrical/Electronics Engineering or allied subjects with minimum qualification
marks of 70 % or CGPA of 7.0 and above, in aggregate of all semesters
Click Here To Apply
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